Hydra

Hydra is a multi-level, hierarchical design planning solution that combines designer expertise with automation to enable users to evaluate design feasibility of advanced-node, multimillion-cell designs. Hydra delivers better floorplans, faster results and handles the biggest designs. It is fully integrated into the Talus® RTL-to GDSII flow and also offered as a standalone solution. Predictable handoff to physical implementation is realized through: out-of-the-box reference flows that accelerate floorplan prototyping; advanced hierarchy aware physical optimization and constraint budgeting to accurately predict timing; and integration of common analysis engines within a unified data model, enabling designers to reliably achieve design closure.

• Out-of-the-Box (OOTB) reference flows allow quick and easy adoption. The channel-style, near-abutment, full-abutment, black-box, repeated-block and multi-power domains reference flows can be combined in any hybrid approach.
• Black-box prototyping provides early analysis capability for logic designers.
• Design scalability is enabled through repeated-block methodology.
• Design feasibility results are derived from advanced hierarchy aware capabilities for physical partitioning, macro placement, soft block shaping and global topology planning of signals, clocks and pins, providing optimal quality-of-results vs. runtime tradeoffs.
• Slack-proportionate time budgeting (re-budgeting) delivers more accurate budgets than traditional methods through continuous refinement based on physical topology, timing criticality of partitions and block implementation.
• Multi-level hierarchical design system manages size and complexity of big chips.
• Powerful and easy-to-use GUI speeds design debug and exploration.
• Integration into the Talus RTL-to-GDSII design flow, common analysis engines and unified data model enhance productivity, provide ease of use, improve data management and ensure correlation with the implementation flow.