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Hydra is a multi-level, hierarchical design planning solution that combines designer expertise with automation to enable users to evaluate design feasibility of advanced-node, multimillion-cell designs. Hydra delivers better floorplans, faster results and handles the biggest designs. It is fully integrated into the Talus® RTL-to GDSII flow and also offered as a standalone solution. Predictable handoff to physical implementation is realized through: OOTB reference flows that accelerate floorplan prototyping; advanced hierarchy aware physical optimization and constraint budgeting to accurately predict timing; and integration of common analysis engines within a unified data model, enabling designers to reliably achieve design closure.
The consumer electronics market continues to demand more functionality at a lower cost. To meet these demands, designs must be migrated to advanced nodes, power consumption must be reduced and design cycles must be shortened. Design teams are expected to implement these larger, more complex chips with existing design teams. By providing critical feedback on feasibility at strategic points in the flow, Hydra enables designers to address the size, complexity and time-to-market challenges of advanced designs.
Traditional tasks such as hierarchical design management, design partitioning, floorplanning and time budgeting are becoming more difficult. Hydra employs a progressive implementation strategy where the optimization effort is aligned to the requirements of the specific design phase. Strategic checkpoints allow design teams to evaluate early netlist quality, floorplan routability and performance goals.
Front-End EvaluationThe initial checkpoint in the Hyrda Feasibility Flow is the Front-end Evaluation. This enables design teams to evaluate the physical topology and timing. Based on initial netlists designers can assess how the logical structures are placed in the physical floorplan. Major timing issues are also identified. With this information upfront, logic designers can make intelligent RTL architecture tradeoffs when the relative cost of such changes is still low.
Congestion EvaluationFloorplan quality and routability are evaluated at the Congestion Evaluation stage. Low-effort global optimization is performed along with initial planning for clocks, power and signals. Optimization and planning are both hierarchy aware and timing driven, enabling Hydra to accurately account for area and routing resources. The assessment of floorplan quality and analysis of congestion allows designers to modify the floorplan prior to spending a significant amount of time on detailed implementation.
Timing Evaluation The Timing Evaluation stage allows design teams to evaluate timing of the design against the performance goals. At this stage detailed global planning for partitions, pin assignments, clocks, power and signals is complete. The go/no-go decision on timing can be made based on accurate information for congestion, boundary timing and clock metrics for the entire design. Changes required to the floorplan, netlist or constraints can be identified during this last stage before handoff to final implementation.
The Hydra Design Feasibility Flow allows intelligent evaluation of the design at critical stages, providing design teams with increased confidence that the resulting floorplan and timing predictions will enable design closure following detailed implementation.
Hydra’s Feasibility Flow provides strategic checkpoints that allow design teams to evaluate early netlist quality, floorplan routability and performance goals.
Hydra provides a black-box methodology for early design planning and prototyping. This methodology allows the designer to start prototyping very early in the design cycle while the block-level RTL is still being defined. The black-box model contains boundary, pin and timing information which is utilized in creating a prototype of the chip-level design. The chip-level prototype provides early feedback on area and timing to logic designers, eliminating top-level surprises. As a result, RTL issues can be identified and resolved early in the RTL definition stage.
The Hydra repeated-block methodology provides extensive control of shaping, pin assignment, budgeting and physical orientations required for block reuse in designs where scalability is a critical requirement. Hydra’s advanced intuitive shaping capability ensures repeated blocks have consistent floorplan shapes and macro placements. The global pin assignment provides a unified set of pin constraints for repeated blocks.
Budgeted constraints are properly derived for critical phases across all the repeated blocks. Multiple orientations are permitted for repeated blocks allowing for optimized placement within the floorplan. Compute resources required for block implementation are significantly reduced because blocks are synchronized to a master implementation, enabling design scalability through block reuse.
Hydra provides design teams with native reference flows for a range of methodologies including channel style, near abutment, full abutment, black box, repeated block and multi-power domains. Today’s complex designs require a combination of methodologies to meet complex design requirements. Hydra is not restricted to a single design style. The hybrid approach provided by Hydra allows designs to be constrained in the most relevant way to meet performance, power and area requirements.
Unlike traditional floorplanning products that require the logic or physical designer to prepare a floorplan manually, Hydra automatically generates a high-quality floorplan at the end of RTL synthesis from an incoming netlist. This floorplan is driven by virtually flat placement of logic cells, Relative Floorplanning Constraints™, timing- and congestion-driven macro placement, and various production-proven techniques used by expert physical designers that are captured in the automated decision-making process.
Hydra eliminates the need to manually partition designs into multiple sub-blocks, or to manually perform block shaping, pin placement, clock-tree creation and power-grid planning. All such tasks are performed automatically, including partitioning for multiple power domains, improving productivity, eliminating the potential for introducing errors and delivering the highest quality of results. The automated macro placer that is integrated with the block shaper generates a fully legal macro placement while minimizing the wirelength and keeping strongly connected macros together.
While automating the key aspects of floorplanning, Hydra also enables easy input and transfer of design data. Relative Floorplanning Constraints, one of the techniques used to direct the tool and also to reuse data, retains the floorplan with minimal changes from one iteration to the next, allowing the designer to maintain familiarity with the floorplan as the design evolves over time. This repeatability and focus on localized changes to the floorplan provide significant advantages because they enable the designer to monitor physical changes such as die area or routability congestion caused by changes in the architecture, additional functionality in RTL, or changes in timing or power constraints. With conventional manual approaches to floorplanning, such changes may delay design delivery.
Hydra’s slack-proportionate budgeting is dependent on the portion of the segment path delay relative to the overall delay of the hierarchical path. Negative slack allocation is handled gracefully by distributing slack proportionately over the path segments. The budgeting process utilizes Magma’s patented GlassBox™ abstraction technique which provides accurate timing and physical models of design blocks while allowing top-level chip implementation to be performed with the same accuracy as if the complete blockdata was part of the top level, but without consuming the memory required to keep all the block details. In completing top-level time budgeting with GlassBox abstracts, delays include propagated clock trees and on-chip variation (OCV) push-down with common path minimization. Timing paths are not reduced to a lumped delay but include the full path from register to register, even when traversing through the hierarchy and glue logic. Improved algorithms provide more accurate delay calculation through a more extensive C effective calculation. This capability enables Hydra to provide highly accurate top-level timing. The re-budgeting flow provides an iterative means of improving budgeting accuracy using post-blockimplementation information. Implemented blocks are abstracted into GlassBox abstracts and reused at the top level. Hydra can also output complete SDC constraints for all blocks post budget, enabling a clean hand off to a thirdparty implementation tool.
Hydra provides automated planning and implementation of power and clock structures while considering IR drop. For hierarchical designs, power plans are done at the top level as well as pushed through the hierarchical boundary, including fixing of the pin locations and proper density of the power grid.
Clock planning predetermines insertion delays at the top level and pushes them down to block level. The delay budgeting takes into account OCV and clock-pin placement to maximize common paths, enabling generation of accurate timing constraints and avoiding hold-time violations at the top level. Thus, the physical partitions can be frozen before the blocks are implemented and no reassembly is necessary.
The complexity and size of today’s designs require a system with the capacity to handle 50M cells or more. Design teams are challenged to maintain current resource levels as block sizes increase significantly. The need to partition the design into multiple levels of hierarchy is quickly becoming a requirement. Hydra natively manages multi-level hierarchical designs. Traditional design planning products have been limited to managing a single level of hierarchy resulting in runtime challenges and accuracy issues due to abstraction. The hierarchy aware optimization capabilities in Hydra look through the design hierarchically while making tradeoffs on critical decisions driving the implementation. This accurate view through the design data is necessary to drive a convergent optimization flow.
Design planning and prototyping is an interactive process. Using Hydra’s powerful visualization tool, designers can browse the logical hierarchy and guide partitioning decisions needed for floorplanning. Block-level colorization and connectivity-driven visualizations such as fly-lines and clockdomain distribution provide valuable architecture and constraint improvement information. Slack-based timing histograms of critical paths in the built-in timing visualizer allow designers to quickly locate timing problems through direct cross-probing of the layout, floorplan, schematic and RTL. Such analysis readily leads to identification of missing constraints or exceptions such as false paths or multicycle paths. In addition, the GUI provides other useful features such as channel overutilization and underutilization, and early IR-drop analysis when used with Talus Power Pro and congestion maps, all of which help design convergence by providing early feedback.
Cross-probing accelerates quality improvement.
Hydra operates on the same unified data model as the Talus Design and Talus Vortex full-chip implementation products, providing seamless integration from prototyping to implementation. After the block-level implementation is completed using Talus, the blocks are abstracted into GlassBox models and then reassembled at the top level to close the chip. Hydra also supports a package-aware chip planning solution enabling I/O planning and placement tradeoffs for both peripheral and flip-chip packages.
Technology Features
• Automated design planning, prototyping and floorplanning • Timing-driven, virtually flat concurrent placement of macros and standard cells • Automatic physical partitioning with soft-macro placement and shaping • Interactive soft-macro placing and shaping including support for rectilinear blocks • Congestion-aware automated macro placer for flat as well as full-chip hierarchical floorplanning • Creation of Relative Floorplanning Constraints • Timing driven, multi-threaded, hierarchy aware global routing • Global-route-driven pin assignment and optimization • Automatic power grid synthesis and power push-down • Logic hierarchy colorization • Global time budgeting and timing push-down/pull-up; SDC support • Complete low-effort, tunable physical synthesis and optimization flow • Ability to handle mixed or partial netlists, black boxes and IP • Complete SDC-constraints output post budgeting to enable clean handoff • Flip-chip I/O planning and RDL routing • Placement control using blockages and clearances • Feed-through push-down and feed-through tunnel support • Manual intervention/guidance allowed during the flow • Timing reports and cross-probe timing paths across the RTL, schematic and layout • Utilization control/feedback • Selective grouping/flattening of hierarchy for placement • CPF/UPF-driven multi-domain low-power flows Inputs • Volcano™ (Magma format) • Verilog netlist • DEF (floorplan), LEF, GDSII • SDC, SPEF, .lib • CPF, UPF Outputs • Volcano (Magma format) • Verilog netlist • DEF (floorplan), LEF, GDSII • SDC, SPEF/DSPF, .lib