Chip Planning

Design engineers must make changes in the design specification throughout the implementation phase. In traditional flows, once the RTL, timing and physical constraints are incorporated, substantial manual effort is required to propagate changes into the hierarchy, floorplan, size and shape of physical partitions and pad locations. For SoC designs at 65 nanometers (nm) and below, designers need an automatic floorplan synthesis methodology that addresses all aspects of hierarchical design planning, reduces time-consuming manual work, prevents the introduction of new errors – especially for changes that must be made late in the design phase – and ensures design closure.

• Hydra is a multi-level, hierarchical design planning solution that combines designer expertise with automation to enable users to evaluate design feasibility of advanced-node, multimillion-cell designs. Hydra delivers better floorplans, faster results and handles the biggest designs. It is fully integrated into the Talus® RTL-to GDSII flow and also offered as a standalone solution. Predictable handoff to physical implementation is realized through: out-of-the-box reference flows that accelerate floorplan prototyping; advanced hierarchy aware physical optimization and constraint budgeting to accurately predict timing; and integration of common analysis engines within a unified data model, enabling designers to reliably achieve design closure.